As the lateral dimensions of interconnect structures continue to decrease, the ability to fabricate conductive vias without voids or seams has become extremely challenging. Conventional methods for fabricating interconnect structures involve lining a via hole (which is etched in an ILD (inter-level dielectric) layer) with a conformal barrier layer and a seed layer, followed by copper (Cu) deposition process such as electroplating to fill the via hole with copper. With decreases in the lateral dimensions, the use of a barrier layer and a seed layer leave little volume within the via holes for copper to be deposited by electroplating. As barrier layers are critical in BEOL (back-end-of-line) structures to prevent diffusion of the interconnect metallization into the material of the ILD layer (e.g., low-k dielectric material) or the underlying silicon, techniques are needed which can properly fill interconnect vias having high aspect ratios (height/width), e.g., aspect ratio that is 5 or greater. Approaches such as direct plating of copper on conventional liner materials, without the need for a seed layer, requires specialized plating baths. Although Cu direct plating on ruthenium (Ru) layers has been demonstrated, ruthenium alone is insufficient to act as a barrier to copper diffusion and a secondary barrier layer is required. Atomic layer deposition (ALD) or chemical-vapor deposition (CVD) techniques have been used to fill vias due to their improved conformality, but the use of such techniques results in vias that have much higher impurities than those corresponding to physical vapor deposition (PVD) approaches.